[ Best Paper of This Month ]

Journal of the Korean Society of Manufacturing Technology Engineers - Vol. 28, No. 4, pp.203-209

ISSN: 2508-5107 (Online)

Print publication date 15 Aug 2019

Received 08 Jul 2019 Accepted 13 Aug 2019

DOI: https://doi.org/10.7735/ksmte.2019.28.4.203

대면적 패널 패키징의 휨 해석

설희승^a ; 최연주^a ; 박정미^a ; 김성걸^a^{, *}

Warpage Analysis of a Panel Level Packaging

Hee Seung Seol^a ; Yeon Ju Choi^a ; Jung Mi Park^a ; Seong Keol Kim^a^{, *}

aDepartment of Mechanical System Design Engineering, Seoul National University of Science and Technology, 232, Gongneung-ro, Nowon-gu, Seoul 01811, Korea

Correspondence to: ^*Tel.: +82-2-970-6855 Fax: +82-2-974-8270 E-mail address: rhett@seoultech.ac.kr (Seong Keol Kim).

Abstract

Panel Level Packaging (PLP) is a next-generation semiconductor packaging technology which has productivity and cost competitiveness. However, warpage issue is needed to be solved for successful product which occurs during packaging process. Warpage is occurred by a coefficient of thermal expansion (CTE) difference between each material, and this warpage should be minimized. In this study, warpage issue of the PLP induced by molding process and detaching process is investigated. Warpage simulation and optimization are carried out by the ANSYS Workbench. In order to figure out which constituent material critically affects warpage problem, single element is adjusted in the range of properties. After then, the selected influential elements are adjusted to figure out optimized values for meeting the process requirement of warpage.

Keywords:

Panel level package, Warpage, ANSYS workbench, Constituent material, Coefficient of thermal expansion, Optimization

Acknowledgments

본 연구는 서울과학기술대학교 교내 일반과제 연구비 지원으로 수행되었습니다.

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