[ Papers ]

Journal of the Korean Society of Manufacturing Technology Engineers - Vol. 29, No. 2, pp.107-111

ISSN: 2508-5107 (Online)

Print publication date 15 Apr 2020

Received 25 Feb 2020 Revised 23 Mar 2020 Accepted 10 Apr 2020

DOI: https://doi.org/10.7735/ksmte.2020.29.2.107

3D-FOWLP에서 TMV (Through Mold Via) 유형(Cu-Via, EMC Filling Via)에 따른 열기계적 특성 시뮬레이션 분석

차지훈^a ; 송규^b ; 박만진^b ; 박상용^c ; 이재천^c ; 이성혁^c ; 장동영^a^{, b}^{, *}

Simulation Analysis of Thermal-mechanical Characteristics According to Type of Through Mold Via Technology in 3D Fan-out Wafer Level Packaging

Ji-Hoon Cha^a ; Kyu Song^b ; Man-Jin Park^b ; Sang-Yong Park^c ; Jae-Cheon Lee^c ; Sung-Hyuk Lee^c ; Dong-Young Jang^a^{, b}^{, *}

aDept. of Manufacturing Systems and Design Engineering, Seoul National University of Science and Technology
bKorea Electronics-Machinery Convergence Technology Institute
cNepes Co., Ltd

Correspondence to: ^*Tel.: +82-2-970-6450 E-mail address: dyjang@seoultech.ac.kr (DongYoung Jang).

Abstract

Currently, Through mold via (TMV) technology is being actively researched for 3D-Intergrated Circuit stacking in fan-out wafer level packaging (FOWLP). However, because of problems, such as extrusion, cracking, and warping of the Cu materials forming the via, its mass production process is difficult. Moreover, sudden temperature changes when using the chips cause heat fatigue in the TMV. To overcome this problem, the Epoxy molding compound (EMC) filling via (EFV) is being developed to form a thin Cu via through a deposition process and then fill the interior of the via with EMC. Through simulations, this study analyzed the thermal-mechanical properties of the TMV in the 3D-FOWLP according to the type of TMV (Cu via and EFV) to minimize the thermal stress and deformation generated when using the chip. Consequently, EFV exhibits better thermal-mechanical properties in comparison with those of the Cu via when the 3D-FOWLP is deformed by heat.

Keywords:

FOWLP, MCP, TMV (Through Mold Via), EFV (EMC Filling Via), Warpage simulation, Package stacking

Acknowledgments

이 연구는 산업통산자원부 산업 기술혁신사업의 지원을 받아 수행된 연구 결과입니다[20000868, FO package를 이용한 인공지능 3D-IC 제조공정 기술].

References

Roh, M. H., Lee, J. H., Jung, J. P., Kim, W. J., 2014, Effect of Thermal Shock on Cu Extrusion of TSV for Three-dimensional Packaging, Korean J. Met Mater, 52:6 459-465. [https://doi.org/10.3365/KJMM.2014.52.6.459]
Seol, H. S., Choi, Y. J., Park, J. M., Kim, S. K., 2019, Warpage Analysis of a Panel Level Packaging, J. Korean Soc. Manuf. Technol. Eng., 28:4 203-209. [https://doi.org/10.7735/ksmte.2019.28.4.203]
Kan, K., Oi, Y., Fujii, Y., Miwa, M., 2016, The Novel Liquid Molding Compound for Fan-out Wafer Level Package, International Conference on Electronics Packaging (ICEP), IEEE, 557-561. [https://doi.org/10.1109/ICEP.2016.7486889]
Lee, M. K., Jeoung, J. W., Ock, J. Y., Choa, S. H., 2014, Numerical Analysis of Warpage and Reliability of Fan-out Wafer Level Package, Journal of the Microelectronics & Packaging Society, 21:1 31-39. [https://doi.org/10.6117/kmeps.2014.21.1.031]
Lee, H. S., Kim, K. H., Choa, S. H., 2012, Warpage and Stress Simulation of Bonding Process-Induced Deformation for 3D Package Using TSV Technology, Journal of the Korean Society for Precision Engineering, 29:5 563-571. [https://doi.org/10.7736/KSPE.2012.29.5.563]
Ko, J. Y., 2018, viewed 25 August 2018, Samsung Mass-produces Automotive D-RAM that Can Withstand Temperatures of 125 Degrees, <www.hankyung.com/economy/article/2018042590081, >.
Jeoung, H. S., 2014, Thermo-mechanical Reliability of TSV Structure for 3D Stacked Semiconductor Package, A master’s thesis on engineering, Seoul National University of Science And Technology, Republic of Korea.