Journal Archive

Journal of the Korean Society of Manufacturing Technology Engineers - Vol. 28 , No. 4

[Paper List] [Go to Volume List]


[ Best Paper of This Month ]
Journal of the Korean Society of Manufacturing Technology Engineers - Vol. 28, No. 4, pp. 203-209
Abbreviation: J. Korean Soc. Manuf. Technol. Eng.
ISSN: 2508-5107 (Online)
Print publication date 15 Aug 2019
Received 08 Jul 2019 Accepted 13 Aug 2019
DOI: https://doi.org/10.7735/ksmte.2019.28.4.203
대면적 패널 패키징의 휨 해석
설희승^a ; 최연주^a ; 박정미^a ; 김성걸^a^{, *}

Warpage Analysis of a Panel Level Packaging
Hee Seung Seol^a ; Yeon Ju Choi^a ; Jung Mi Park^a ; Seong Keol Kim^a^{, *}
aDepartment of Mechanical System Design Engineering, Seoul National University of Science and Technology, 232, Gongneung-ro, Nowon-gu, Seoul 01811, Korea
Correspondence to : ^*Tel.: +82-2-970-6855 Fax: +82-2-974-8270 E-mail address: rhett@seoultech.ac.kr (Seong Keol Kim).



Funding Information ▼ Seoul National University of Science and Technology

Abstract

Panel Level Packaging (PLP) is a next-generation semiconductor packaging technology which has productivity and cost competitiveness. However, warpage issue is needed to be solved for successful product which occurs during packaging process. Warpage is occurred by a coefficient of thermal expansion (CTE) difference between each material, and this warpage should be minimized. In this study, warpage issue of the PLP induced by molding process and detaching process is investigated. Warpage simulation and optimization are carried out by the ANSYS Workbench. In order to figure out which constituent material critically affects warpage problem, single element is adjusted in the range of properties. After then, the selected influential elements are adjusted to figure out optimized values for meeting the process requirement of warpage.


Keywords: Panel level package, Warpage, ANSYS workbench, Constituent material, Coefficient of thermal expansion, Optimization

Acknowledgments

본 연구는 서울과학기술대학교 교내 일반과제 연구비 지원으로 수행되었습니다.

References


1.	Su, M., Cao, L., Lin, T., Chen, F., Li, J., Chen, C., Tian, G., 2018, Warpage Simulation and Experimental Verification for 320mm×320mm Panel Level Fan-out Packaging based on Die-first Process, Microelectronics Reliability, 83 29-38.
2.	Chiu, T., Yeh, E., 2017, Warpage Simulation for the Reconstituted Wafer used in Fan-out Wafer Level Packaging, Microelectronics Reliability, 80 14-23.
3.	Liu, H., Liu, Y., Ji, J., Liao, J., Chen, A., Chen, Y., Kao, N., Lai, Y., 2014, Warpage Characterization of Panel Fan-out (P-FO) Package, 2014 ECTC, 1750-1754.
4.	Hou, F., Lin, T., Cao, L., Liu, F., Li, J., Fan, X., Zhang, G., 2017, Experimental Verification and Optimization Analysis of Warpage for Panel-Level Fan-Out Package, IEEE Transactions on Components, Packaging and Manufacturing Technology, 7:10 1721-1728.
5.	OZEN ENGINEERING, viewed May 2018, <https://www.ozeninc.com/>.
6.	Kim, B., 2015, Understanding and Prospecting of Semiconductor Packaging Technique, Issue & Tech (JBTP), 42 1-24.
7.	Braun, T., Becker, K., Voges, S., Thomas, T., Kahle, R., Bader, V., Bauer, J., Aschenbrenner, R., Lang, K., 2014, Challenges and Opportunities for Fan-Out Panel Level Packaging (FOPLP), 2014 IMPACT, 154-157.
8.	Lee, M., 2014, Study of Warpage Optimization for Fan-Out Wafer Level Package, Master Dissertation, Seoul National University of Science and Technology, Republic of Korea.
9.	Lin, T., Hou, F., Liu, H., Pan, D., Chen, F., Li, J., Zhang, H., Cao, L., 2016, Warpage Simulation and Experiment for Panel Level Fan-Out Package, 2016 ICSJ, 129-131.
*10.*	ANSYS Help.
*11.*	Che, F., Ho, D., Ding, M. Z., Daniel, R. M., 2016, Study on Process Induced Wafer Level Warpage of Fan-Out Wafer Level Packaging, 2016 IEEE 66th ECTC, 1879-1885.
*12.*	Che, F., Ho, D., Ding, M. Z., Zhang, X., 2015, Modeling and Design Solutions to Overcome Warpage Challenge for Fan-Out Wafer Level Packaging (FO-WLP) Technology, 2015 IEEE 17th EPTC, 1-8.
*13.*	Lau, J. H., Li, M., Tian, D., Fan, N., Kuah, E., Kai, W., Li, M., Hao, J., Cheung, Y. M., Li, Z., Kim, H. T., Beica, R., Taylor, T., Ko, C., Yang, H., Chen, Y., Lim, S. P., Lee, N. C., Ran, J., Xi, C., Wee, K. S., Yong, Q., 2017, Warpage and Thermal Characterization of Fan-Out Wafer-Level Packaging, IEEE Transactions on Components, Packaging and Manufacturing Technology, 7:10 1729-1738.
*14.*	Takekoshi, M., Nishido, K., Okada, Y., Suzuki, N., Nonaka, T., 2017, Warpage Suppression during FO-WLP Fabrication Process, 2017 IEEE 67th ECTC, 902-908.
*15.*	Corning, viewed 23 July 2019, <https://www.corning.com/kr/ko.html>.
*16.*	Matweb, viewed 7 August 2019, <http://www.matweb.com>.